1. Field of the Invention
The present invention relates to reduction of power consumption of a thin-film semiconductor circuit constituted of crystalline silicon. The invention also relates to reduction of power consumption of a drive circuit of an active matrix display device that is constituted of crystalline silicon.
The invention also relates to an ion doping technique for a semiconductor material, and a manufacturing method of a semiconductor and a semiconductor device using that ion doping technique.
Further, the invention relates to reduction of a leak current while a thin-film transistor (hereinafter abbreviated as “TFT”) is off.
2. Description of the Related Art
In recent years, extensive studies have been made of the active matrix display device using a liquid crystal. In the active matrix display device, a switching element is provided for each pixel and a signal coming from an image signal line is supplied to each pixel through the corresponding switching element.
Although previously TFTs using an amorphous silicon semiconductor were used as the switching element, in recent years TFTs have been developed which use a crystalline silicon semiconductor (i.e., a silicon semiconductor including crystal components) having a high operation speed.
However, in a TFT using a crystalline silicon semiconductor, the leak current (off-current) that flows when the gate electrode is reversely biased is larger than in a TFT using an amorphous silicon semiconductor.
This phenomenon, which is believed due to the existence of crystal grain boundaries, is the most serious problem, because it deteriorates the characteristics of a crystalline silicon-based circuit constituting an active matrix display device and increases its power consumption.
In the case of an N-channel TFT, when VGS (source-gate voltage of the TFT) is negative, a leak current is determined by currents flowing through PN junctions that are formed between a P-type layer that is induced in the surface of a semiconductor thin film and N-type layers of source and drain regions. Because of many traps existing in the semiconductor thin film (particularly in grain boundaries), these PN junctions are incomplete, likely causing a relatively large junction leak current.
The reason why the leak current increases as the gate electrode is negatively biased more deeply is that the carrier concentration of the P-type layer formed in the surface of the semiconductor thin film increases, which lowers the energy barrier height of the PN junction, which in turn causes an electric field concentration, resulting in increase of the junction leak current.
The leak current that is caused by the above mechanism strongly depends on the source-drain voltage; that is, the leak current rises sharply as the voltage applied between the source and the drain of a TFT is increased. For example, in some cases, a leak current with a source-drain voltage of 10 V is more than 10 times, rather than 2 times, larger than that with a source-drain voltage of 5 V.
The above nonlinearity also depends on the gate voltage. In general, the leak current difference between the above two cases is larger when the gate electrode is reversely biased more deeply (in an N-channel TFT, when a larger negative voltage is applied).
Typical examples of products using the active matrix display device include a notebook-type personal computer and a portable information terminal. However, in current models of these products, the active matrix display device is responsible for most of the total power consumption. Therefore, to satisfy the need of long-term driving by a battery, it is now desired to reduce the power consumption of the active matrix display device.
However, even where a peripheral drive circuit of an active matrix display device are constituted of CMOS (complementary metal-oxide-semiconductor) TFTs, large leak currents flow through the P-channel TFTs in an off state, making the power consumption of the entire circuit large.
In the case of a high-resolution, large-screen type active matrix display device, long gate lines of the screen cause a problem that there is a delay until the TFT of a selected pixel is turned on. A wiring resistance Rwire and a wiring capacitance Cwire of a gate line are approximated asRwire=ρ·L/(W·T)Cwire=nox·W·L/H where                ρ: resistivity of a wiring material        
L: wiring length
W: wiring width
T: wiring film thickness
nox: dielectric constant of a field oxide film.
A delay twire, which is equal to a time constant Rwire·Cwire, is expressed astwire=ρ·nox·L2/(T·H).
This equation indicates that the signal delay due to a wiring line is proportional to the square of the wiring length.
Conventionally, the signal delay due to a wiring line is prevented by reducing the wiring length of gate lines by providing a gate line drive circuit on both sides of the active matrix display device. However, this measure is not sufficient.